The present invention relates to photolithographic processing, and in particular to methods of controlling the formation of objects on a semiconductor wafer.
Most modem integrated circuits are created by photolithographic techniques whereby selected portions of a silicon wafer are exposed to illumination light. The particular areas that are exposed on the wafer are generally determined by a mask or reticle having opaque and clear areas that block or pass the illumination light.
As the size of the features to be created on the wafer become smaller and smaller, the features can become distorted due to optical effects, such as diffraction or destructive interference of the light passing through the mask or reticle. Another distortion can occur as a result of setting the exposure time/intensity for the wafer. FIG. 1 illustrates a portion of a semiconductor mask or reticle having a number of elements 10 that are relatively widely spaced or isolated from one another. For example, these elements may represent interconnect wires to be created within an integrated circuit. Additionally, the mask or reticle includes a number of elements 12 that are closely grouped with one another. If the exposure of the mask or reticle is set such that the isolated elements 10 are properly imaged on the wafer, then it often happens that the relatively closely grouped elements 12 will be incorrectly exposed. Conversely, if the exposure of the mask or reticle is set such that the closely grouped elements 12 are properly formed on the wafer, then the isolated elements 10 will be incorrectly exposed. In many instances, it is virtually impossible to select an exposure of the mask or reticle that will optimize the formation of closely grouped and isolated circuit elements on a wafer.
To address the problems discussed above, the present invention is a method for controlling the creation of closely spaced objects on a wafer during photolithographic processing. A mask or reticle has a substantially uniform pattern of features disposed thereon and the exposure of the mask or reticle is chosen such that objects created by the uniform feature pattern is optimized. The uniform pattern of features on the mask/reticle creates a corresponding uniform pattern of objects on a wafer. Selected objects can then be used as desired to provide the desired functionality.
In one embodiment of the invention, the substantially uniform feature pattern comprises a number of uniformly spaced lines that form interconnect wires on an integrated circuit. Interconnect wires of specific lengths are created by terminating the lines at desired points on the mask or reticle. Alternatively, wire of specific length can be created by exposing the wafer at the desired endpoints of the wires.
In another embodiment of the invention, the circuit elements to be created are gate electrodes. A mask or reticle has substantially uniform pattern of strips that create gate electrodes over semiconductor wells. Individual gate electrodes are made by terminating the lines at desired locations either on the mask or reticle itself, or on the wafer.